The present invention relates to a semiconductor device and manufacturing method for same. More particularly, the present invention relates to a device isolation layer formed in a semiconductor device, and a method for forming same this layer using oxygen ion implantation.
As semiconductor devices become ever more highly integrated, active devices formed on the semiconductor substrate have decreased to a size near or below 1 micron. This dramatic reduction in size has also taken place with respect to device isolation regions which electrically separate the active devices. The size and nature of a typical device isolation region, which is formed early in the manufacturing process of the overall semiconductor device, influence the size of the active regions subsequently formed on the semiconductor substrate, and margins between such devices. This fact requires semiconductor manufacturers to add a planarizing step to remove step differences, i.e., surface undulations, in many field insulating layers. The conventional method of local oxidation of silicon (LOCOS) presently used by semiconductor manufacturers has several disadvantages including the "bird's beak phenomenon" caused by lateral oxidation, the formation of crystal defects in the substrate caused by heat stress, and undesired redistribution of implanted impurities used as a channel stopper. Accordingly, LOCOS fails to attain the improved electrical characteristics necessary for higher integration of semiconductor devices.
To overcome the disadvantages attendant to LOCOS, a trench isolation method has been proposed. In this method, a field oxide layer is not formed by thermal oxidation as in LOCOS. Thus, the disadvantages associated with the thermal oxidation step in LOCOS are somewhat reduced.
However, the trench isolation method is not without its own problems. For example, formation of the trench to a depth greater than the designed depth creates crystal defects in the silicon substrate. Additionally, when insulation material is filled into a broad trench, the insulation material often has an uneven profile. Such an uneven profile leads to unstable device isolation characteristics and structural step differences in the trench pattern.
The foregoing isolation methods, LOCOS and trench, will be explained in greater detail with reference to FIGS. 1A and 1B, and FIGS. 2A, 2B, 2C, and 2D.
FIGS. 1A and 1B are cross-sectional views illustrating the conventional LOCOS isolation method. Referring to FIG. 1A, a pad oxide layer 3 and a silicon nitride layer 5 are sequentially formed on a semiconductor substrate 1. A portion of silicon nitride layer 5 in a field region 9 is then removed by photolithography. Thereafter, a channel stopper ion 7 is implanted into field region 9. Thus, an active region 11 is isolated by field regions 9.
Referring now to FIG. 1B, the semiconductor substrate having field regions 9 and active region 11 is placed in an oxidation furnace and subjected to thermal oxidation under predetermined conditions to form a field oxide layers 13 from field regions 9. A channel stopper region 15 of impurities redistributed by thermal diffusion is formed under each field oxide layer 13. Also, during thermal oxidation, the semiconductor substrate adjacent to field region 9 is oxidized in a direction towards the active region 11 which leads to the bird's beak phenomenon. Thus, the "actual" field region 20 extends laterally into regions 19 to form the bird's beak, rather than remaining within the originally intended field region 17. The bird's beak phenomenon may be seen as an undesired and uncontrolled expansion of the field region beyond its intended design rule margins. This phenomenon adversely impacts attempts to maintain the fine patterns required in highly integrated semiconductor devices.
Additionally, in LOCOS, the field oxide layer is thermally grown to not less than 3,000 .ANG. in thickness. Accordingly, the potential for crystal defect caused by the stress occurring around the boundary of the active region and the silicon nitride layer which is selectively covered on the semiconductor substrate can lead to increased leakage current between devices.
FIGS. 2A-2D are cross-sectional views sequentially illustrating the conventional trench isolation method.
Referring to FIG. 2A, a pad oxide layer 2 of about 240 .ANG. in thickness is formed over semiconductor substrate 1 by the thermal oxidation. A silicon nitride layer 4 of about 1,500 .ANG. thickness and a thermal oxide layer 6 of about 1,000 .ANG. thickness are sequentially formed by low pressure chemical vapor deposition (LPCVD), and the thermal oxide layer over a field region is then removed by photolithography.
Referring to FIG. 2B, by using the thermal oxide layer remaining over the active region as an etching mask, silicon nitride 4 and pad oxide layer 2 is subjected to reactive ion etching and semiconductor substrate 1 is then dry etched to form a trench. At this time, a narrow trench region and a broad trench region coexist in the substrate in accordance with the design rule of the semiconductor device.
Thereafter, a side wall oxide layer 8 is formed inside the trench by the thermal oxidation, and polysilicon 10 is then deposited to a thickness not less than 5,000 .ANG., and is anisotropically etched to fill the trench with polysilicon. At this time, the narrow trench region is completely filled, but the polysilicon in the broad trench region is sunken in its center region. That is, varying loading effects occur wherein each trench depending upon the trench's size, and these loading effects determine the "filler" profile of the polysilicon.
Referring to FIG. 2C, a field oxide layer 12 is formed on the polysilicon filling the trench using a thermal oxidation process. Note that "filled" profile of the broad trench region remains sunken in its center region.
Referring to FIG. 2D, the buffer layers including the thermal oxide layer, the silicon nitride layer and the pad oxide layer, are wet etched using a buffered oxide etchant (B.O.E). The B.O.E. may comprise a mixed solution of fluoroammonium and fluorohydrogen (7:1), and phosphoric acid solution. A sacrificial oxide layer (not shown) is thereafter grown and then wet etched, whereby the formation of the device isolation process is completed.
In the trench isolation method, a gate line and bit line may be shorted, or an electrical interconnection characteristic be deteriorated by sunken center region phenomenon (indicated by the letter G in FIG. 2D) of polysilicon filling the broad trench region. At a minimum, this phenomenon reduces product yield.
The bird's beak phenomenon (indicated by the letter R in FIG. 2D) occurs during the formation of the field oxide layer and limits the reduction of the device isolation region size. Also, when the thermal oxide layer of the buffer layer is etched, the field oxide layer is simultaneously etched to a predetermined thickness. Therefore, the field oxide layer should be increased in thickness in consideration of the process margin. Accordingly, the bird's beak phenomenon is deepened, thereby precluding the desired higher integration of the semiconductor device.
In response to the foregoing problems arising in the trench isolation method, an improved trench isolation method incorporating a chemical-mechanical polishing (CMP) step has previously been proposed. This improved trench method has been considered an ideal method for completely filling the trench, and thereafter etching the insulating material overfilling the trench, because the insulation material refilled in the trench is removed in the horizontal direction. However, the added CMP step also has disadvantages such as the "dishing" phenomenon, wherein the center of the broad trench region becomes hollowed out into a dish shape when the width of the wide trench is greater than several mm. Such adverse affects create unstable device isolation characteristics and the structural step differences.